Mram 8

Objectives: Azithromycin treatment of Chlamydia trachomatis (CT) may not be adequate to treat concomitant Mycoplasma genitalium (MG) infection, and particularly if MG has macrolide resistance-associated mutations (MG-MRAMs). We estimated prevalence of coinfections of CT with MG carrying MRAM, and risk factors for MG-MRAM among a sexual health clinic population. Study design and setting: Among symptomatic and STI-contact clinic attendees in London, prevalence of CT-MG coinfection and MG-MRAM were estimated using nucleic acid amplification testing and Sanger sequencing, respectively, and their associated risk factors analysed using logistic regression. Results: MG prevalence was 7.5% (23/307), 17.3% (30/173), and 11.4% (8/70) in females, men who have sex with women (MSW) and men who have sex with men (MSM), respectively; MG coinfection in CT-infected participants represented 28.0% (7/25), 13.5% (5/37), 0.0% (0/0), respectively. Presence of MG-MRAM was 39.1% (9/23) in female swabs, 70.0% (21/30) in MSW urine and 83.3% (5/6) in MSM rectal swabs. In multivariate analyses, coinfection with another STI was strongly associated with MG-MRAM (OR: 7.19; 95% CI: 2.4 to 21.5). Conclusion: A significant proportion of participants in our study of symptomatic patients and STI contacts were infected with macrolide-resistant MG, suggesting that testing for MG and MRAM, for MG positives, might be clinically useful. The findings also suggest services explore potential benefits of testing CT positive samples for MG in these patient groups. Where MG testing is not available, potential high rates of MG coinfection should be borne in mind when considering azithromycin in the treatment of CT among STI contacts and symptomatic patients.

Implementations of artificial neural networks that borrow analogue techniques could potentially offer low-power alternatives to fully digital approaches1-3. One notable example is in-memory computing based on crossbar arrays of non-volatile memories4-7 that execute, in an analogue manner, multiply-accumulate operations prevalent in artificial neural networks. Various non-volatile memories-including resistive memory8-13, phase-change memory14,15 and flash memory16-19-have been used for such approaches. However, it remains challenging to develop a crossbar array of spin-transfer-torque magnetoresistive random-access memory (MRAM)20-22, despite the technology's practical advantages such as endurance and large-scale commercialization5. The difficulty stems from the low resistance of MRAM, which would result in large power consumption in a conventional crossbar array that uses current summation for analogue multiply-accumulate operations. Here we report a 64 × 64 crossbar array based on MRAM cells that overcomes the low-resistance issue with an architecture that uses resistance summation for analogue multiply-accumulate operations. The array is integrated with readout electronics in 28-nanometre complementary metal-oxide-semiconductor technology. Using this array, a two-layer perceptron is implemented to classify 10,000 Modified National Institute of Standards and Technology digits with an accuracy of 93.23 per cent (software baseline: 95.24 per cent). In an emulation of a deeper, eight-layer Visual Geometry Group-8 neural network with measured errors, the classification accuracy improves to 98.86 per cent (software baseline: 99.28 per cent). We also use the array to implement a single layer in a ten-layer neural network to realize face detection with an accuracy of 93.4 per cent.

Physical unclonable function (PUF), a hardware-efficient approach, has drawn a lot ofattention in the security research community for exploiting the inevitable manufacturing variabilityof integrated circuits (IC) as the unique fingerprint of each IC. However, analog PUF is notrobust and resistant to environmental conditions. In this paper, we propose a digital PUF-basedsecure authentication model using the emergent spin-transfer torque magnetic random-accessmemory (STT-MRAM) PUF (called STT-DPSA for short). STT-DPSA is an original secure identityauthentication architecture for Internet of Things (IoT) devices to devise a computationallylightweight authentication architecture which is not susceptible to environmental conditions.Considering hardware security level or cell area, we alternatively build matrix multiplication orstochastic logic operation for our authentication model. To prove the feasibility of our model, thereliability of our PUF is validated via the working windows between temperature interval (-35 °C,110 °C) and Vdd interval [0.95 V, 1.16 V] and STT-DPSA is implemented with parameters n = 32,i = o = 1024, k = 8, and l = 2 using FPGA design flow. Under this setting of parameters, an attackerneeds to take time complexity O(2256) to compromise STT-DPSA. We also evaluate STT-DPSA usingSynopsys design compiler with TSMC 0.18 um process.